1. Field of the Invention
The present invention relates to an ATM cell multiplexer, and in particular to an ATM cell multiplexer connected between terminal equipments and an ATM switchboard.
xe2x80x9cATM (Asynchronous Transfer Mode)xe2x80x9d technology is expected as a communication technology for realizing a multi-media society, and has been developed for fast data used in an inter-computer communication etc.
However, as seen from recent ATM forums, a network is demanded in the market where the communication protocols of prior art such as for voices, HDLC (High level Data Link) and FR (frame relay) can also be interworked with the ATM technology.
When such a network is constructed, it is useful to set up an ATM cell multiplexer as an apparatus in branch circuit or line system in order to construct an ATM switchboard (ATM switch) as a key network and to increase the accommodation efficiency of circuits with terminal equipments.
2. Description of the Related Art
FIG. 52 shows a general arrangement of such an ATM cell multiplexer. An ATM cell multiplexer generally designated by reference numeral 2 is adapted to assemble data received from a terminal equipment generally designated by reference numeral 1 in the form of an ATM cell, to send the data to an ATM switchboard generally designated by reference numeral 3 through a trunk circuit, and to disassemble the ATM cell (hereinafter simply referred to as the cell) which is received through the trunk circuit from the ATM switchboard 3 and transmitted to the terminal equipment 1.
In this ATM cell multiplexer, although strict traffic control (QOS control) proper to the ATM protocol is demanded, the prior art ATM switchboard and ATM cell multiplexer has installed an ATM switch (not shown) to perform the traffic control.
However, the ATM switch is disadvantageous in that the manufacturing cost is highly expensive and the control of the software/hardware is complicated, requiring a large-sized unit.
While an ATM cell multiplexer such as shown in the Japanese Patent Laid-open Publication No.5-91126 has been proposed, it requires the output capacity for the whole circuits because of adopting a method in which cells are simply multiplexed.
In addition, an ATM cell multiplexer such as shown in the Japanese Patent Laid-open Publication No.7-38569 uses a plurality of CLAD units which include both functions of cellulating data received from the terminal equipments and decellulating the cells received from the trunk circuits. However, when the cells through a plurality of connections mutually compete within the ATM cell multiplexer, some of the cells must be delayed or stood by to make the cells communicate without any collision in each of service categories such as CBR (Constant Bit Rate), VBR (Variable Bit Rate), or UBR (Unspecific Bit Rate).
This is not particularly allowed in a service category like CBR in which a time delay is strictly prohibited.
It is accordingly an object of the present invention to provide an ATM cell multiplexer which can simply and inexpensively assemble or disassemble cells without causing a time delay between terminal equipments and an ATM switchboard.
To achieve the above-mentioned object, an ATM cell multiplexer according to the present invention comprises a plurality of CLAD units, connected in parallel on an ATM bus so that ATM cells are assembled and disassembled between terminal equipments and the ATM switchboard, each including a cell holding portion, a communication controller, and a cell terminal portion which are all mutually connected with a Utopia Level 2 interface (hereinafter, occasionally referred to simply as xe2x80x9cUtopia Level 2xe2x80x9d), and an ATM bus scheduler for an ATM bus control connected to the CLAD units through the ATM bus; the cells from the cell terminal portion being held in the cell holding portion through the Utopia Level 2 under control of the communication controller for a cell transfer in the up direction from the terminal equipments to the ATM switchboard, and the ATM bus scheduler making the cell holding portion transmit the cells to the ATM bus by assigning a transmission right for every cell holding portion of the CLAD units in accordance with a preset schedule table based on at least one of predetermined service categories and a traffic control corresponding to a traffic quantity; and the cells being broadcast from the ATM bus to the cell holding portion of each CLAD unit for a cell transfer in the down direction from the ATM switchboard to the terminal equipments, and the communication controller making the cell holding portion transfer the cells to the cell terminal portion through the Utopia Level 2 to decide whether or not the cells are addressed to itself.
Namely, in order to efficiently and easily multiplex the ATM cell transmitted from a plurality of CLAD units, the ATM cell multiplexer according to the present invention, as schematically shown in FIG. 1, is provided therein with an ATM bus 12, to which CLAD units 13-1-13-n (hereinafter occasionally referred to as xe2x80x9c13xe2x80x9d) are connected in parallel to enable the cell to be transmitted to a trunk circuit or a backup circuit thereof from the CLAD units 13 through a trunk circuit controller 14 or a backup circuit controller 15, respectively.
Also, in order to provide an opportunity of transmitting the cells out of the CLAD units 13, an ATM bus scheduler 11 is connected to the ATM bus 12. This ATM bus scheduler 11 performs cell multiplexing operations and traffic controls without installing any ATM switch by controlling the transmission/reception of the cells on the ATM bus 12.
In this case, xe2x80x9cschedulexe2x80x9d means that the ATM bus scheduler 11 assigns a transmission right of cells to each of the CLAD units 13 so that the cells may be transmitted to the ATM switchboard (see FIG. 1) from the CLAD units 13 through the trunk circuit.
The CLAD units 13 accommodate terminal circuits connected to the terminal equipments (see FIG. 1), and assemble data received from the terminal equipments in the form of cell which is to be transmitted to the ATM bus 12. The cells received from the ATM switchboard through the trunk circuit are also transmitted to the ATM bus 12 and each of the CLAD units 13.
The role of the ATM bus 12 is an interface between an ATM layer (a network layer) in the CLAD units 13 and a physical layer by a physical layer terminal portion (PHY) 10 in the circuit controllers 14 and 15. For this function, the CLAD units 13 are provided with an ATM cell terminal portion 20 represented by an SAR (Segmentation And Reassembly) including a function of assembling and disassembling ATM cells.
Also, as the above-mentioned interface a Utopia Level 2 is adopted, which is a standard interface prescribed by the ATM forum and is known as what achieves data transfer with the physical layer terminal portion 10 individually connected to the ATM cell terminal portion 20, as shown in FIG. 2. Hereinafter, apart from the arrangement in FIG. 1, the Utopia Level 2 per se will be described referring to FIGS. 2-4.
Transmission of Cells from ATM Layer to Physical Layer Terminal Portion 10: see FIG. 3
A signal TxCav from the physical layer terminal portion 10 to the ATM cell terminal portion 20 of the CLAD units 13 is one for indicating that the physical layer terminal portion 10 can receive the cells.
When a transmitting cell exists inside the ATM cell terminal portion 20 and the signal TxCav indicates that the physical layer terminal portion 10 is in a reception enable state, based on a clock signal CLK, the ATM cell terminal portion 20 transmits cell data TxData composed of data Data01-Data53 with a signal TxEnb asserted or enabled (an inverted TxEnb deasserted or disabled).
A signal TxSoc is also asserted at the time of the head data01 in the cell data TxData. The cell data TxData is transmitted while the signal TxEnb is asserted.
Transmission of Cells from Physical Layer Terminal Portion 10 to ATM Layer: see FIG. 4
A signal RxCav from the physical layer terminal portion 10 to the ATM cell terminal portion 20 is one for indicating that there is a transmitting cell in the physical layer terminal portion 10. If the ATM cell terminal portion 20 itself can receive, or is a reception enable state of cell, it asserts a signal RxEnb or deasserts an inverted RxEnb to receive cell data RxData composed of Data01-Data53. The signal TxSoc is also asserted at the time of the head Data01 in the cell data RxData. The physical layer terminal portion 10 also asserts a signal RxSoc at the time of the head Data01 in the cell data RxData to be transmitted. Only while the signal RxEnb is being asserted, the physical layer terminal portion 10 transmits the cell data Data01-Data53.
Since various kinds of parts having an Utopia Level 2 which is a standard of the ATM forum are available on the market, it is of great advantage to use the Utopia Level 2 in aspect of both cost and function. However, in the arrangement in FIG. 1 it is quite difficult to use the Utopia Level 2 as it is between the physical layer terminal portion 10 and the ATM bus 12, and between the ATM bus 12 and the ATM cell terminal portion 20.
Namely, the Utopia Level 2 is one through which the ATM layer controls the physical layer terminal portion 10 and allows a single cell to be disassembled minutely in octet for the transmission thereof Therefore, if the Utopia Level 2 is connected to the ATM bus as shown in FIG. 2, following problems arise: {circle around (1)} The time when the cell transfer is completed is not guaranteed; {circle around (2)} Accordingly, there is no guarantee of realizing the same bus scheduling as the ATM bus scheduler 11 has supposed.
Therefore, in the present invention, some devices are made to the arrangement in FIG. 1 as noted below and schematically shown in FIG. 5 in order that a bus connection is executed without any trouble in the Utopia Level 2 of the arrangement shown in FIG. 1.
First of all, in each of the CLAD units 13, FIFO""s 21 and 22 are provided which form a cell holding portion between the ATM cell terminal portion 20 and the ATM bus 12 in addition to the ATM cell terminal portion 20 having the Utopia Level 2 which is the standard of the ATM forum. The output data from the ATM cell terminal portion 20 are accumulated by at least a single cell in the FIFO 21, and the output data from the physical layer terminal portion 10 are accumulated by at least a single cell in the FIFO 22.
In addition, an ATM communication controller 23 is provided which has the Utopia Level 2 UIF for controlling the transfer of data between the FIFO""s 21, 22 and the ATM cell terminal portion 20.
FIG. 6 shows an arrangement of a conversion between the Utopia Level 2 UIF which lies between the ATM communication controller 23 and the ATM cell terminal portion 20 and an interface PIF which is proper for the present invention and lies between the ATM communication controller 23 and the ATM bus 12.
It is to be noted that the ATM bus 12 is arranged in accordance with the Utopia Level 2 in consideration of the compatibility with the Utopia Level 2 UIF. Accordingly, the ATM bus 12, that is the ATM bus scheduler 11, and the physical layer terminal portion 10 are equivalent to each other.
FIGS. 7 and 8 respectively show a time chart between the ATM communication controller 23 and the ATM bus 12 (the ATM scheduler 11), and the schematic operation of the ATM bus 12 according to the present invention will be described referring to FIGS. 6-8.
Transmission of Cells from ATM Bus 12 to ATM Cell Terminal Portion 20: see FIG. 7
In this case, the ATM communication controller 23 monitors a DSOC signal on the ATM bus 12 which indicates that the heads of cells are transmitted to the ATM bus 12 from the trunk circuit, that is the physical layer terminal portion 10. When the DSOC signal is asserted through the interface PIF or when the inverted DSOC signal is deasserted as shown in the figure, the ATM communication controller 23 recognizes it as the heads of cells and takes the following 53-byte cell data DData (Data01-Data53) into the FIFO 22.
After having taken the cell data into the FIFO 22, the ATM communication controller 23 transfers the cell to the ATM cell terminal portion 20 according to the procedure of the above-mentioned Utopia Level 2 UIF shown in FIG. 2, and returns the signal indicating the completion of the transfer to the ATM bus 12 through the interface PIF.
Transmission of Cells from ATM Cell Terminal Portion 20 to ATM Bus 12: see FIG. 8
At least one of the cells from the ATM cell terminal portion 20 is written in the FIFO 21 through the Utopia Level 2 UIF under the control of the ATM communication controller 23. After the accumulation of a single cell in the FIFO 21, the ATM communication controller 23 outputs a transmission request signal (REQ) to the ATM bus 12 upon receiving a TXE signal from the ATM bus 12 which indicates that the trunk circuit can receive the cell.
When a GNT (transmission enable) signal is received from the ATM bus 12 through the interface PIF, a selecting signal BRI#xENB of the circuit is firstly asserted, or the inverted signal is deasserted as shown in the figure. Then, a USOC signal indicating the head of cell is asserted through the interface PIF, or the inverted signal is deasserted as shown in the figure while at the same time the cell data UData (Data01-Data53) are transmitted through the interface PIF.
Such an arrangement enables the following functions:
{circle around (1)} Management of the transmission/reception of cell by the ATM scheduler 11 can be easily executed because a single cell in the data on the ATM bus 12 is continuously transmitted;
{circle around (2)} Management for the ATM bus 12 can be executed only by the ATM bus scheduler 11 apart from the ATM cell terminal portion 20, for the simplification of control;
{circle around (3)} Supposed scheduling of the ATM bus scheduler 11 is made possible and the control of the transmission right to the CLAD units is made possible according to the service categories, which will be described later, prescribed by the ATM forum.
The ATM bus scheduler 11 controls the ATM bus 12 as follows:
(1) When the cells are transmitted to the ATM bus 12 from a plurality of the CLAD units 13, the ATM bus scheduler 11 avoids the competition of the cells on the ATM bus 12;
(2) In order to transmit the cells to the ATM switchboard through the trunk circuit from the CLAD units 13 according to the service categories (CBR, rt (real time)-VBR, nrt (non-real time)-VBR, UBR) prescribed by the ATM forum, the ATM bus scheduler 11 gives the transmission right to each of the CLAD units 13 based on the service categories. Only when being given a transmission right by the ATM bus scheduler 11, the CLAD units 13 transmit the cell to the ATM bus 12;
(3) The ATM bus scheduler 11 controls the cell transmission in agreement with the traffic quantity so that the transmission rate should not exceed a predetermined maximum cell rate (PCR) and average cell rate (SCR) when CLAD unit 13 transmit the cells.
It is to be noted that the above-mentioned ATM bus scheduler can control the transmission/reception of the cells by assigning the cells in the up and down directions equally on the ATM bus in case that a single trunk circuit is connected to the ATM switchboard.
Alternatively, the ATM bus scheduler can also control the reception of a plurality of cells within a single time slot in the down direction while a single cell in the up direction in case that a plurality of trunk circuits are connected to the ATM switchboard.
When there are a plurality of the above-mentioned trunk circuits and the physical speeds are mutually different, the ATM bus scheduler can select a detour or non-detour per each CLAD unit by thinning out a set interval in a memory table which determines the order of the transmission right given by the ATM bus.
It is possible that the ATM bus scheduler can extend the number of the trunk circuits by assigning the reception right per each CLAD unit in accordance with a preset schedule table by the traffic control which complies with a predetermined service category or the traffic quantity with respect to the cells not only in the up direction but also in the down direction.
It is also possible that an SVC call setting controller is provided besides the CLAD units to control the call set protocol, and to set in the CLAD units a connection ID determined on the trunk circuit, thereby connecting to the ATM switchboard.
The SVC call setting controller may set a virtual connection ID and have an SOFT-PVC function prescribed by the PNNI.
The above service categories may comprise CBR, rt-VBR, nrt-VBR, and UBR. The schedule table may be composed of a main table including all service categories except UBR and a sub table including service categories with a lower priority for the transmission right. The ATM bus scheduler may assign the transmission right on the basis of the sub table only when the CLAD units in the main table have abandoned the transmission rights.
The main table may be prepared so that the transmission rights for the CLAD units are equally allocated to every time slot in a frame in the order of CBR, rt-VBR and nrt-VBR and in the registration order of the CLAD units.